patch-2.2.18 linux/drivers/video/aty128.h

• Lines: 83
• Date: Wed Nov 8 23:00:35 2000
• Orig file: v2.2.17/drivers/video/aty128.h
• Orig date: Sat Sep 9 18:42:46 2000

diff -u --new-file --recursive --exclude-from /usr/src/exclude v2.2.17/drivers/video/aty128.h linux/drivers/video/aty128.h
@@ -43,10 +43,12 @@
 #define OVR_CLR					0x0230
 #define OVR_WID_LEFT_RIGHT			0x0234
 #define OVR_WID_TOP_BOTTOM			0x0238
+#define LVDS_GEN_CNTL				0x02d0
 #define DDA_CONFIG				0x02e0
 #define DDA_ON_OFF				0x02e4
 #define VGA_DDA_CONFIG				0x02e8
 #define VGA_DDA_ON_OFF				0x02ec
+#define CRTC2_GEN_CNTL				0x03f8
 #define OV0_SCALE_CNTL				0x0420
 #define SUBPIC_CNTL				0x0540
 #define PM4_BUFFER_OFFSET			0x0700
@@ -218,6 +220,7 @@
 
 #define PLL_WR_EN				0x00000080
 
+/* PLL registers */
 #define CLK_PIN_CNTL				0x0001
 #define PPLL_CNTL				0x0002
 #define PPLL_REF_DIV				0x0003
@@ -236,6 +239,7 @@
 #define AGP_PLL_CNTL				0x0010
 #define FCP_CNTL				0x0012
 #define PLL_TEST_CNTL				0x0013
+#define POWER_MANAGEMENT			0x002f
 
 #define PPLL_RESET				0x01
 #define PPLL_ATOMIC_UPDATE_EN			0x10000
@@ -266,7 +270,8 @@
 #define DAC_MASK				0xFF000000
 #define DAC_BLANKING				0x00000004
 #define DAC_RANGE_CNTL				0x00000003
-#define PALETTE_ACCESS_CNTL			0x00000020
+#define DAC_PALETTE_ACCESS_CNTL			0x00000020
+#define DAC_PDWN				0x00008000
 
 /* GEN_RESET_CNTL bit constants */
 #define SOFT_RESET_GUI				0x00000001
@@ -338,5 +343,43 @@
 #define DP_SRC_RECT				0x00000200
 #define DP_SRC_HOST				0x00000300
 #define DP_SRC_HOST_BYTEALIGN			0x00000400
+
+/* LVDS_GEN_CNTL constants */
+#define LVDS_BL_MOD_LEVEL_MASK			0x0000ff00
+#define LVDS_BL_MOD_LEVEL_SHIFT			8
+#define LVDS_BL_MOD_EN				0x00010000
+#define LVDS_DIGION				0x00040000
+#define LVDS_BLON				0x00080000
+#define LVDS_ON					0x00000001
+#define LVDS_DISPLAY_DIS			0x00000002
+#define LVDS_PANEL_TYPE_2PIX_PER_CLK		0x00000004
+#define LVDS_PANEL_24BITS_TFT			0x00000008
+#define LVDS_FRAME_MOD_NO			0x00000000
+#define LVDS_FRAME_MOD_2_LEVELS			0x00000010
+#define LVDS_FRAME_MOD_4_LEVELS			0x00000020
+#define LVDS_EN					0x00000080
+
+/* CRTC2_GEN_CNTL constants */
+#define CRTC2_EN				0x02000000
+
+/* POWER_MANAGEMENT constants */
+#define	PWR_MGT_ON				0x00000001
+#define PWR_MGT_MODE_MASK			0x00000006
+#define PWR_MGT_MODE_PIN			0x00000000
+#define PWR_MGT_MODE_REGISTER			0x00000002
+#define PWR_MGT_MODE_TIMER			0x00000004
+#define PWR_MGT_MODE_PCI			0x00000006
+#define PWR_MGT_AUTO_PWR_UP_EN			0x00000008
+#define PWR_MGT_ACTIVITY_PIN_ON			0x00000010
+#define PWR_MGT_STANDBY_POL			0x00000020
+#define PWR_MGT_SUSPEND_POL			0x00000040
+#define PWR_MGT_SELF_REFRESH			0x00000080
+#define PWR_MGT_ACTIVITY_PIN_EN			0x00000100
+#define PWR_MGT_KEYBD_SNOOP			0x00000200
+#define PWR_MGT_TRISTATE_MEM_EN			0x00000800
+#define PWR_MGT_SELW4MS				0x00001000
+#define PWR_MGT_SLOWDOWN_MCLK			0x00002000
+
+#define PMI_PMSCR_REG				0x60
 
 #endif /* REG_RAGE128_H */