patch-2.4.20 linux-2.4.20/arch/sparc64/kernel/cpu.c

• Lines: 116
• Date: Thu Nov 28 15:53:12 2002
• Orig file: linux-2.4.19/arch/sparc64/kernel/cpu.c
• Orig date: Sun Mar 25 18:14:21 2001

diff -urN linux-2.4.19/arch/sparc64/kernel/cpu.c linux-2.4.20/arch/sparc64/kernel/cpu.c
@@ -31,22 +31,24 @@
  */
 struct cpu_fp_info linux_sparc_fpu[] = {
   { 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
-  { 0x22, 0x10, 0, "UltraSparc II integrated FPU"},
+  { 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
   { 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
   { 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
   { 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
   { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
+  { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
 };
 
 #define NSPARCFPU  (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info))
 
 struct cpu_iu_info linux_sparc_chips[] = {
   { 0x17, 0x10, "TI UltraSparc I   (SpitFire)"},
-  { 0x22, 0x10, "TI UltraSparc II  (BlackBird)"},
+  { 0x22, 0x10, "TI UltraSparc I   (SpitFire)"},
   { 0x17, 0x11, "TI UltraSparc II  (BlackBird)"},
   { 0x17, 0x12, "TI UltraSparc IIi"},
   { 0x17, 0x13, "TI UltraSparc IIe"},
   { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
+  { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
 };
 
 #define NSPARCCHIPS  (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info))
@@ -63,48 +65,63 @@
 
 void __init cpu_probe(void)
 {
-	int manuf, impl;
-	unsigned i, cpuid;
-	long ver, fpu_vers;
-	long fprs;
+	unsigned long ver, fpu_vers, manuf, impl, fprs;
+	int i, cpuid;
 	
 	cpuid = hard_smp_processor_id();
 
-	fprs = fprs_read ();
-	fprs_write (FPRS_FEF);
-	__asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]" : "=&r" (ver) : "r" (&fpu_vers));
-	fprs_write (fprs);
+	fprs = fprs_read();
+	fprs_write(FPRS_FEF);
+	__asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
+			      : "=&r" (ver)
+			      : "r" (&fpu_vers));
+	fprs_write(fprs);
 	
-	manuf = ((ver >> 48)&0xffff);
-	impl = ((ver >> 32)&0xffff);
+	manuf = ((ver >> 48) & 0xffff);
+	impl = ((ver >> 32) & 0xffff);
 
-	fpu_vers = ((fpu_vers>>17)&0x7);
+	fpu_vers = ((fpu_vers >> 17) & 0x7);
 
-	for(i = 0; i<NSPARCCHIPS; i++) {
-		if(linux_sparc_chips[i].manuf == manuf)
-			if(linux_sparc_chips[i].impl == impl) {
-				sparc_cpu_type[cpuid] = linux_sparc_chips[i].cpu_name;
+ retry:
+	for (i = 0; i < NSPARCCHIPS; i++) {
+		if (linux_sparc_chips[i].manuf == manuf) {
+			if (linux_sparc_chips[i].impl == impl) {
+				sparc_cpu_type[cpuid]
+					= linux_sparc_chips[i].cpu_name;
 				break;
 			}
+		}
 	}
 
-	if(i==NSPARCCHIPS) {
-		printk("DEBUG: manuf = 0x%x   impl = 0x%x\n", manuf, 
-			    impl);
+	if (i == NSPARCCHIPS) {
+		/* Maybe it is a cheetah+ derivative, report it as cheetah+
+		 * in that case until we learn the real names.
+		 */
+		if (manuf == 0x3e &&
+		    impl > 0x15) {
+			impl = 0x15;
+			goto retry;
+		} else {
+			printk("DEBUG: manuf[%lx] impl[%lx]\n",
+			       manuf, impl);
+		}
 		sparc_cpu_type[cpuid] = "Unknown CPU";
 	}
 
-	for(i = 0; i<NSPARCFPU; i++) {
-		if(linux_sparc_fpu[i].manuf == manuf && linux_sparc_fpu[i].impl == impl)
-			if(linux_sparc_fpu[i].fpu_vers == fpu_vers) {
-				sparc_fpu_type[cpuid] = linux_sparc_fpu[i].fp_name;
+	for (i = 0; i < NSPARCFPU; i++) {
+		if (linux_sparc_fpu[i].manuf == manuf &&
+		    linux_sparc_fpu[i].impl == impl) {
+			if (linux_sparc_fpu[i].fpu_vers == fpu_vers) {
+				sparc_fpu_type[cpuid]
+					= linux_sparc_fpu[i].fp_name;
 				break;
 			}
+		}
 	}
 
-	if(i == NSPARCFPU) {
-		printk("DEBUG: manuf = 0x%x  impl = 0x%x fsr.vers = 0x%x\n", manuf, impl,
-			    (unsigned)fpu_vers);
+	if (i == NSPARCFPU) {
+		printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
+		       manuf, impl, fpu_vers);
 		sparc_fpu_type[cpuid] = "Unknown FPU";
 	}
 }