patch-1.3.65 linux/include/asm-alpha/apecs.h
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- Lines: 113
- Date:
Sat Feb 17 09:19:42 1996
- Orig file:
v1.3.64/linux/include/asm-alpha/apecs.h
- Orig date:
Tue Dec 26 04:45:40 1995
diff -u --recursive --new-file v1.3.64/linux/include/asm-alpha/apecs.h linux/include/asm-alpha/apecs.h
@@ -74,63 +74,63 @@
* These are used to program memory timing,
* configure memory and initialise the B-Cache.
*/
-#define APECS_IOC_GCR (IDENT_ADDR + 0x180000000UL)
-#define APECS_IOC_EDSR (IDENT_ADDR + 0x180000040UL)
-#define APECS_IOC_TAR (IDENT_ADDR + 0x180000060UL)
-#define APECS_IOC_ELAR (IDENT_ADDR + 0x180000080UL)
-#define APECS_IOC_EHAR (IDENT_ADDR + 0x1800000a0UL)
-#define APECS_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
-#define APECS_IOC_LDxLAR (IDENT_ADDR + 0x1800000e0UL)
-#define APECS_IOC_LDxHAR (IDENT_ADDR + 0x180000100UL)
-#define APECS_IOC_GTR (IDENT_ADDR + 0x180000200UL)
-#define APECS_IOC_RTR (IDENT_ADDR + 0x180000220UL)
-#define APECS_IOC_VFPR (IDENT_ADDR + 0x180000240UL)
-#define APECS_IOC_PDLDR (IDENT_ADDR + 0x180000260UL)
-#define APECS_IOC_PDhDR (IDENT_ADDR + 0x180000280UL)
+#define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL)
+#define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL)
+#define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL)
+#define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL)
+#define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL)
+#define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
+#define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL)
+#define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL)
+#define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL)
+#define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL)
+#define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL)
+#define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL)
+#define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL)
/* Bank x Base Address Register */
-#define APECS_IOC_B0BAR (IDENT_ADDR + 0x180000800UL)
-#define APECS_IOC_B1BAR (IDENT_ADDR + 0x180000820UL)
-#define APECS_IOC_B2BAR (IDENT_ADDR + 0x180000840UL)
-#define APECS_IOC_B3BAR (IDENT_ADDR + 0x180000860UL)
-#define APECS_IOC_B4BAR (IDENT_ADDR + 0x180000880UL)
-#define APECS_IOC_B5BAR (IDENT_ADDR + 0x1800008A0UL)
-#define APECS_IOC_B6BAR (IDENT_ADDR + 0x1800008C0UL)
-#define APECS_IOC_B7BAR (IDENT_ADDR + 0x1800008E0UL)
-#define APECS_IOC_B8BAR (IDENT_ADDR + 0x180000900UL)
+#define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL)
+#define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL)
+#define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL)
+#define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL)
+#define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL)
+#define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL)
+#define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL)
+#define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL)
+#define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL)
/* Bank x Configuration Register */
-#define APECS_IOC_B0BCR (IDENT_ADDR + 0x180000A00UL)
-#define APECS_IOC_B1BCR (IDENT_ADDR + 0x180000A20UL)
-#define APECS_IOC_B2BCR (IDENT_ADDR + 0x180000A40UL)
-#define APECS_IOC_B3BCR (IDENT_ADDR + 0x180000A60UL)
-#define APECS_IOC_B4BCR (IDENT_ADDR + 0x180000A80UL)
-#define APECS_IOC_B5BCR (IDENT_ADDR + 0x180000AA0UL)
-#define APECS_IOC_B6BCR (IDENT_ADDR + 0x180000AC0UL)
-#define APECS_IOC_B7BCR (IDENT_ADDR + 0x180000AE0UL)
-#define APECS_IOC_B8BCR (IDENT_ADDR + 0x180000B00UL)
+#define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL)
+#define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL)
+#define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL)
+#define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL)
+#define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL)
+#define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL)
+#define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL)
+#define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL)
+#define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL)
/* Bank x Timing Register A */
-#define APECS_IOC_B0TRA (IDENT_ADDR + 0x180000C00UL)
-#define APECS_IOC_B1TRA (IDENT_ADDR + 0x180000C20UL)
-#define APECS_IOC_B2TRA (IDENT_ADDR + 0x180000C40UL)
-#define APECS_IOC_B3TRA (IDENT_ADDR + 0x180000C60UL)
-#define APECS_IOC_B4TRA (IDENT_ADDR + 0x180000C80UL)
-#define APECS_IOC_B5TRA (IDENT_ADDR + 0x180000CA0UL)
-#define APECS_IOC_B6TRA (IDENT_ADDR + 0x180000CC0UL)
-#define APECS_IOC_B7TRA (IDENT_ADDR + 0x180000CE0UL)
-#define APECS_IOC_B8TRA (IDENT_ADDR + 0x180000D00UL)
+#define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL)
+#define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL)
+#define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL)
+#define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL)
+#define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL)
+#define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL)
+#define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL)
+#define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL)
+#define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL)
/* Bank x Timing Register B */
-#define APECS_IOC_B0TRB (IDENT_ADDR + 0x180000E00UL)
-#define APECS_IOC_B1TRB (IDENT_ADDR + 0x180000E20UL)
-#define APECS_IOC_B2TRB (IDENT_ADDR + 0x180000E40UL)
-#define APECS_IOC_B3TRB (IDENT_ADDR + 0x180000E60UL)
-#define APECS_IOC_B4TRB (IDENT_ADDR + 0x180000E80UL)
-#define APECS_IOC_B5TRB (IDENT_ADDR + 0x180000EA0UL)
-#define APECS_IOC_B6TRB (IDENT_ADDR + 0x180000EC0UL)
-#define APECS_IOC_B7TRB (IDENT_ADDR + 0x180000EE0UL)
-#define APECS_IOC_B8TRB (IDENT_ADDR + 0x180000F00UL)
+#define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL)
+#define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL)
+#define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL)
+#define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL)
+#define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL)
+#define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL)
+#define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL)
+#define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL)
+#define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL)
/*
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen, slshen@lbl.gov
with Sam's (original) version of this